When Instruction Execution Is Delayed By One State - Renesas H8S Series Hardware Manual

Section 6 PC Break Controller (PBC)
6.3.5

When Instruction Execution is Delayed by One State

While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
ROM or RAM.
• When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
Rev. 6.00 Mar 15, 2006 page 94 of 570
REJ09B0211-0600