Exception Handling Operation; Exception Vector Table - Hitachi H8S/2338 Series Hardware Manual

2.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as
follows:
1. The program counter (PC), condition code register (CCR), and extend register (EXR) are
pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
2.1.3

Exception Vector Table

The exception sources are classified as shown in figure 2-1. Different vector addresses are
assigned to different exception sources.
Table 2-2 lists the exception sources and their vector addresses.
Exception
sources
In modes 6 and 7, the on-chip ROM available for use after a power-on reset is the 64-kbyte area
comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. In
this case, clearing the EAE bit in BCRL enables the 256-kbyte* area comprising addresses
H'000000 to H'03FFFF to be used.
Note: * Depends on the model. See the relevant reference manual for details.
8
• Reset
• Trace
External interrupts: NMI, IRQ7 to IRQ0
• Interrupts
Internal interrupts: interrupts from on-chip
supporting modules
• Trap instruction
Figure 2-1 Exception Sources