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3.6.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts except NMI are disabled and the next instruction is always
executed.
When the I bit is set by one of these instructions, the new value is valid two states after instruction
execution is completed.
3.6.3
Periods when Interrupts are Disabled
There are periods during which interrupt acceptance by the interrupt controller is disabled.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
3.6.4
Interrupts during Execution of EEPMOV Instruction
The EEPMOV.B instruction and EEPMOV.W instruction differ in their reaction to interrupt
requests.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
The following coding should be used to allow for interrupts generated during execution of an
EEPMOV.W instruction.
L1:
EEPMOV.W
MOV.W
R4,R4
BNE
L1
3.7
DTC and DMAC Activation by Interrupt
3.7.1
Overview
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available. Some models do not have an on-chip DMAC; see the reference manual for the relevant
model for details.
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