E-12 Upper Bat Register - Motorola MPC8240 User Manual

PowerPC Register Set
BEPI
0
BRPN
0
*W and G bits are not defined for IBAT registers. Attempting to write to these bits causes boundedly-undefined results.
Table E-10 describes the bits in the BAT registers.
Table E-10. BAT Registers—Field and Bit Descriptions
Upper/Lower
Bits
BAT
Upper BAT 0–14
Register
15–18
19–29
30
31
Lower BAT 0–14
Register
15–24
25–28
29
30–31
E-16
14 15
Figure E-12. Upper BAT Register
14 15
Figure E-13. Lower BAT Register
Name
BEPI Block effective page index. This field is compared with high-order bits of the
logical address to determine if there is a hit in that BAT array entry.
— Reserved
BL Block length. BL is a mask that encodes the size of the block. Values for
this field are listed in Table E-11.
Vs Supervisor mode valid bit. This bit interacts with MSR[PR] to determine if
there is a match with the logical address.
Vp User mode valid bit. This bit also interacts with MSR[PR] to determine if
there is a match with the logical address.
BRPN This field is used in conjunction with the BL field to generate high-order bits
of the physical address of the block.
— Reserved
WIMG Memory/cache access mode bits
W Write-through
I Caching-inhibited
M Memory coherence
G Guarded
Attempting to write to the W and G bits in IBAT registers causes
boundedly-undefined results.
— Reserved
PP Protection bits for block. This field determines the protection for the block.
MPC8240 Integrated Processor User's Manual
0 000
18 19
0 0000 0000 0
Description
Reserved
BL Vs Vp
29 30 31
Reserved
WIMG* 0 PP
24 25 28 29 30 31