Peripheral Logic Power Management Configuration Registers (Pmcrs); Power Management Configuration Register 1 (Pmcr1)—0X70 - Motorola MPC8240 User Manual

4.3 Peripheral Logic Power Management
Configuration Registers (PMCRs)
The power management configuration registers (PMCRs) control the power management
functions of the peripheral logic. For more information on the power management feature
of both the processor core and the peripheral logic, see Chapter 14, "Power Management."
4.3.1 Power Management Configuration Register 1
(PMCR1)—Offset 0x70
Power management configuration register 1 (PMCR1), shown in Figure 4-5, is a 2-byte
register located at offset 0x70.
LP_REF_EN
NO_SLEEP_MSG
NO_NAP_MSG
Figure 4-5. Power Management Configuration Register 1 (PMCR1)—0x70
Table 4-15 describes the bits of PMCR1.
Table 4-15. Bit Settings for Power Management Configuration
Bits Name
15 NO_NAP_MSG
14 NO_SLEEP_MSG
13 —
12 LP_REF_EN
Peripheral Logic Power Management Configuration Registers (PMCRs)
0 0 0 0 0
15 14 13 12 11
Register 1—0x70
Reset
Value
0 HALT command broadcast—Not supported on the MPC8240.
1 Initialization software must set this bit, indicating that the MPC8240 does not
broadcast a HALT command on the PCI bus before entering the nap mode.
0 Sleep message broadcast.—Not supported on the MPC8240.
1 Initialization software must set this bit, indicating that the MPC8240 does not
broadcast a sleep message command on the PCI bus before entering the
sleep mode.
0 Reserved
0 Low-power refresh
0 Indicates that the MPC8240 does not perform memory refresh cycles when it
is in sleep mode
1 Indicates that the MPC8240 continues to perform memory refresh cycles
when in sleep mode
Chapter 4. Configuration Registers
0
8 7 6 5 4 3 2
Description
Reserved
PM
DOZE
NAP
SLEEP
CKO_MODE
CKO_SEL
1 0
4-17