Cache Coherency - Motorola MPC8240 User Manual

Cache Implementation
Unlike entire cache locking, invalid entries in a locked way are accessible and available for
data placement. As hits to the cache fill invalid entries within a locked way, the entries
become valid and locked. This behavior differs from entire cache locking where nothing is
placed in the cache, even if invalid entries exist in the cache. Unlocked ways of the cache
behave normally.

5.4.3 Cache Coherency

The central control unit (CCU) manages the cache coherency within the MPC8240. It
responds to all accesses generated by the processor core and causes the snooping of the
addresses in the internal buffers as necessary. Also, the CCU generates snoop transactions
on the peripheral logic bus to allow the processor to snoop accesses between the PCI
interface and memory. Refer to Chapter 7, "PCI Bus Interface," for more detailed
information about the internal address and data buffers in the MPC8240.
5.4.3.1 CCU Responses to Processor Transactions
The processor core generates various types of read and write accesses as well as
address-only transactions. Table 5-5 shows all the types of internal transactions performed
by the processor core and the CCU responses.
Table 5-5. CCU Responses to Processor Transactions
Processor Transaction
Read
Read-with-intent-to-modify
Read atomic
Read-with-intent-to-modify-atomic
Write-with-flush
Write-with-kill
Write-with-flush-atomic
sync
eieio
Kill block (generated by dcbz instruction
when the addressed block has either the E
or M bits set)
icbi
Read-with-no-intent-to-cache
Clean
Flush
tlbie
lwarx, reservation set
5-24
Directs read to appropriate interface
Directs read to appropriate interface
Directs read to appropriate interface
Directs read to appropriate interface
Directs write to appropriate interface
Directs write to appropriate interface
Directs write to appropriate interface
CCU buffers are flushed.
CCU buffers are flushed.
CCU buffers are snooped.
CCU buffers are snooped.
Directs read to appropriate interface
CCU takes no further action.
CCU takes no further action.
CCU takes no further action.
CCU takes no further action.
(The MPC8240 does not support atomic
references in PCI memory space.)
MPC8240 Integrated Processor User's Manual
CCU Response