E.1.3.11 External Access Register (Ear) - Motorola MPC8240 User Manual

Implementation-Specific Registers from 603e
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E.1.3.11 External Access Register (EAR)

The EAR is a 32-bit SPR that controls access to the external control facility and identifies
the target device for external control operations. This register can also be accessed by using
the mtspr and mfspr instructions. The EAR is shown in Figure E-21.
E
0 1
The bit settings for the EAR are described in Table E-15.
Table E-15. External Access Register (EAR) Bit Settings
Bit Name
0 E Enable bit
1 Enabled
0 Disabled
If this bit is set, the eciwx and ecowx instructions can perform the specified external
operation. If the bit is cleared, an eciwx or ecowx instruction causes a DSI exception.
1–25 — Reserved
26–31 RID Resource ID
E.2 Implementation-Specific Registers from 603e
The processor core of the MPC8240 includes some implementation-specific SPRs of the
603e processor that are not defined by the PowerPC architecture. Most of these are
described in the MPC603e User's Manual and are implemented in the MPC8240 as
follows:
• MMU software table search registers—DMISS, DCMP, HASH1, HASH2, IMISS,
ICMP, and RPA. These registers facilitate the software required to search the page
tables in memory and should only be accessed when address translation is disabled
(that is, MSR[IR] = 0 and MSR[DR] = 0).
• IABR—This register facilitates the setting of instruction breakpoints.
These registers can be accessed by supervisor-level instructions only. Any attempt to access
these SPRs with user-level instructions results in a supervisor-level exception. The SPR
numbers for these registers are shown in Figure E-1.
E-20
Figure E-20. Decrementer Register (DEC)
000 0000 0000 0000 0000 0000 00
Figure E-21. External Access Register (EAR)
MPC8240 Integrated Processor User's Manual
DEC
Description
31
Reserved
RID
25 26 31