Exception Priorities - Motorola MPC8240 User Manual

Memory Management
Table 5-8. Exceptions and Conditions (Continued)
Exception Vector Offset
Type (hex)
Data store 01200
translation
miss
Instruction 01300
address
breakpoint
System 01400
management
interrupt
Reserved 01500–02FFF

5.5.3 Exception Priorities

The exception priorities for the processor core are unchanged from those described in the
MPC603e User's Manual except for the alignment exception, whose causes are prioritized
as follows:
1. Floating-point operand not word-aligned
2. lmw, stmw, lwarx, or stwcx operand not word-aligned
3. eciwx or ecowx operand misaligned
4. A multiple or string access is attempted with MSR[LE] set.
Also, there is a priority mechanism for all the conditions specific to the MPC8240 that can
cause a machine check exception. These are described in Chapter 13, "Error Handling."
5.6 Memory Management
The following subsections describe the memory management features of the PowerPC
architecture and the MPC8240 implementation.
5.6.1 PowerPC MMU Model
The primary functions of the MMU are:
• to translate logical (effective) addresses to physical addresses for memory accesses
• to provide access protection on blocks and pages of memory
There are two types of accesses generated by the processor core that require address
translation—instruction accesses and data accesses to memory generated by load and store
instructions.
The PowerPC MMU and exception models support demand-paged virtual memory. Virtual
memory management permits execution of programs larger than the size of physical
5-30
A data store translation miss exception is caused when the effective address for a
data store operation cannot be translated by the DTLB, or when a DTLB hit occurs,
and the changed bit in the PTE must be set due to a data store operation.
An instruction address breakpoint exception occurs when the address (bits 0–29) in
the IABR matches the next instruction to complete in the completion unit, and the
IABR enable bit (bit 30) is set.
A system management interrupt is caused when MSR[EE] = 1 and the SMI input
signal is asserted.
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MPC8240 Integrated Processor User's Manual
Causing Conditions