Pci Single-Beat Read Transaction - Motorola MPC8240 User Manual

PCI Bus Transactions
AD[31:0] as data signals. The turnaround cycle is enforced by the target with the TRDY
signal. The target provides valid data at the earliest one cycle after the turnaround cycle.
The target must drive the AD[31:0] signals when DEVSEL is asserted.
During the data phase, the C/BE[3:0] signals indicate which byte lanes are involved in the
current data phase. A data phase may consist of a data transfer and wait cycles. The
C/BE[3:0] signals remain actively driven for both reads and writes from the first clock of
the data phase through the end of the transaction.
A data phase completes when data is transferred, which occurs when both IRDY and TRDY
are asserted on the same clock edge. When either IRDY or TRDY is negated, a wait cycle
is inserted and no data is transferred. The initiator indicates the last data phase by negating
FRAME when IRDY is asserted. The transaction is considered complete when data is
transferred in the last data phase.
Figure 7-3 illustrates a PCI single-beat read transaction. Figure 7-4 illustrates a PCI burst
read transaction.
PCI_SYNC_IN
AD[31:0] ADDR DATA
C/BE[3:0] CMD Byte enables
FRAME
IRDY
DEVSEL
TRDY
Figure 7-3. PCI Single-Beat Read Transaction
Chapter 7. PCI Bus Interface 7-15