Inbound Free_Fifo Tail Pointer Register (Iftpr) - Motorola MPC8240 User Manual

I O Interface
2
Table 9-15 shows the bit settings for the IFHPR.
Table 9-15. IFHPR Field Descriptions—Offset 0x0_0120
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 IFHP All 0s
1–0 — 00

9.3.4.2.4 Inbound Free_FIFO Tail Pointer Register (IFTPR)

PCI masters pick up free MFAs from the inbound free_list FIFO pointed to by the inbound
free_FIFO tail pointer register (IFTPR). The actual PCI reads of MFAs are performed
through the inbound FIFO queue port register (IFQPR). The MPC8240 automatically
increments the IFTP value after every read from IFQPR. Figure 9-12 shows the bits of the
IFTPR.
31
Figure 9-12. Inbound Free_FIFO Tail Pointer Register (IFTPR)
Table 9-16 shows the bit settings for the IFTPR.
Table 9-16. IFTPR Field Descriptions—Offset 0x0_0128
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 IFTP All 0s
1–0 — 00
9.3.4.2.5 Inbound Post_FIFO Head Pointer Register (IPHPR)
PCI masters post MFAs to the inbound post_list FIFO pointed to by the inbound post_FIFO
head pointer register (IPHPR). The actual PCI writes are performed through the inbound
FIFO queue port register (IFQPR). The MPC8240 automatically increments the IPHP value
after every write to IFQPR. Figure 9-13 shows the bits of the IPHPR.
9-16
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Inbound free_FIFO head pointer. The processor maintains the local memory offset
of the head pointer of the inbound free _list FIFO in this field.
R Reserved
QBA
20 19
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Inbound free_FIFO tail pointer. Maintains the local memory offset of the tail pointer
of the inbound free _list FIFO.
R Reserved
MPC8240 Integrated Processor User's Manual
Description
IFTP
Description
Reserved
0 0
2 1 0