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Signal Overview
2.1.1 Signal Cross Reference
The following sections are intended to provide a quick summary of signal functions.
Table 2-1 provides an alphabetical cross-reference to the signals of the MPC8240. It details
the signal name, interface, alternate functions, number of signals, whether the signal is an
input, output, or bidirectional, and finally a pointer to the section in this chapter where the
signal is described.
Signal
AD[31:0]
Address/data
AR[19:12]
ROM address 19–12
1
AS
Address strobe
CAS[0:7]
Column address strobe
0–7
C/BE[3:0]
Command/byte enable
CHKSTOP_IN
Checkstop in
1
CKE
SDRAM clock enable
CKO
Debug clock
CS[0:7]
SDRAM chip select
DA[15:11], DA2
Debug addr [15:11, 2]
DA[10:6]
Debug addr [10:6]
DA5
Debug addr 5
DA4
Debug addr 4
DA3
Debug addr 3
DA1
Debug addr 1
DA0
Debug addr 0
DEVSEL
Device select
DQM[0:7]
SDRAM data qualifier
1
FOE
Flash output enable
FRAME
Frame
GNT[3:0]
PCI bus grant
1
GNT4/DA5
HRST_CPU
Hard reset (processor)
HRST_CTRL
Hard reset (peripheral
logic)
IDSEL
ID select
INTA
Interrupt request
IRDY
Initiator ready
IRQ0
Interrupt 0
IRQ1
Interrupt 1
2-4
Table 2-1. MPC8240 Signal Cross Reference
Signal Name
PCI
Memory
Memory
Memory
PCI
System Control
Memory
Clock
Memory
Debug
Debug
Debug
PCI
Memory
Memory
PCI
PCI
System Control
System Control
PCI
PCI
PCI
EPIC Control
EPIC Control
MPC8240 Integrated Processor User's Manual
Alternate
Interface
Function (s)
—
PAR[0:7]
—
DQM[0:7]
—
—
—
DA1
RAS[0:7]
—
PLL_CFG[0:4]
GNT4
REQ4
PCI_CLK4
CKO
QACK
—
CAS[0:7]
—
—
GNT0: PCI bus
request
GNT4: DA5
—
—
—
—
—
S_INT
S_CLK
Pins
I/O
Section #
32
I/O
2.2.1.3
8
O
2.2.2.11
1
O
2.2.2.18
8
O
2.2.2.2
4
I/O
2.2.1.5
1
I
2.2.5.6
1
O
2.2.2.12
1
O
2.2.7.8
8
O
2.2.2.3
6
O
2.2.5.10.3
5
O
2.2.5.10.3
5
O
2.2.5.10.3
1
I/O
2.2.1.6
8
O
2.2.2.4
1
O
2.2.2.17
1
I/O
2.2.1.7
5
O
2.2.1.2
1
I
2.2.5.1.1
1
I
2.2.5.1.2
1
I
2.2.1.15
1
O
2.2.1.14
1
I/O
2.2.1.8
1
I
2.2.3.1
1
I/O
2.2.3.1
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