Epic Vendor Identification Register (Evi) - Motorola MPC8240 User Manual

Register Definitions
Table 11-7 describes the bit settings for the EICR.
Table 11-7. EICR Field Descriptions—Offset 0x4_1030
Reset
Bits Name
Value
31 — 0
30–28 R 0x4
27 SIE 0
26–0 — All 0s
11.9.4 EPIC Vendor Identification Register (EVI)
The EVI has specific read-only information about the vendor and the device revision.
Figure 11-7 shows the bits in the EVI.
0 0 0 0 0 0 0 0
31
Figure 11-7. EPIC Vendor Identification Register (EVI)
Table 11-8 describes the bit settings for the EVI.
Table 11-8. EVI Register Field Descriptions—Offset 0x4_1080
Bits Name
31–24 —
23–16 STEP
15–8 DEVICE_ID
7–0 VENDOR_ID
11-18
Reserved
Clock ratio. The S_CLK signal is driven by EPIC at a frequency of the SDRAM_CLK
frequency divided by twice the value of this 3-bit field. The reset value of this field is
0x4. At this value, the S_CLK signal operates at 1/8th the frequency of the
SDRAM_CLK signal. The allowable range of values for this field is between 1 and 7
resulting in a clock division ratio between 2 and 14 respectively.
Note that an illegal value could result in spurious vectors returned when in either direct
or serial mode.
Serial interrupt enable. This bit selects whether the MPC8240 IRQ signals are
configured for direct interrupts or serial interrupts. The GCR[M] must be set to 1
(mixed-mode) in order for this bit value to have meaning.
0 Direct interrupts mode
1 Serial interrupts mode
Reserved
STEP
24 23
Reset
Value
All 0s Reserved
0x01 Stepping. This indicates the stepping (silicon revision) for this device.
All 0s Device identification
All 0s Vendor identification. Because this value is zeros, the MPC8240 is
considered to be a generic PIC-compliant device.
MPC8240 Integrated Processor User's Manual
Description
DEVICE_ID
16 15 8 7
Description
Reserved
VENDOR_ID
0