Motorola MPC8240 User Manual page 201

Integrated host processor with integrated pci
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— Floating-point compare
— Floating-point status and control
• Load/store instructions—These include integer and floating-point load and store
instructions.
— Integer load and store
— Integer load and store with byte reverse
— Integer load and store string/multiple
— Floating-point load and store
• Flow control instructions—These include branching instructions, condition register
logical instructions, trap instructions, and other synchronizing instructions that
affect the instruction flow.
— Branch and trap
— Condition register logical
— Primitives used to construct atomic memory operations (lwarx and stwcx.)
— Synchronize
• Processor control instructions—These instructions are used for synchronizing
memory accesses and management of caches, TLBs, and the segment registers.
— Move to/from SPR
— Move to/from MSR
— Instruction synchronize
• Memory control instructions—These provide control of caches, TLBs, and segment
registers.
— Supervisor-level cache management
— User-level cache management
— Segment register manipulation
— TLB management
Note that this grouping of the instructions does not indicate which execution unit executes
a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for
byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Floating-point instructions operate on single-precision (one word) and double-precision
(one double word) floating-point operands. It also provides for word and double-word
operand loads and stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a
computation and then modify the same or another memory location, the memory contents
must be loaded into a register, modified, and then written back to the target location with
Chapter 5. PowerPC Processor Core
Programming Model
5-19

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