11.9.5 Processor Initialization Register (PI)
The processor initialization register (PI) provides a mechanism for the software, through
the EPIC unit, to cause a soft reset of the processor by asserting the sreset signal. Note that
this register is read/write. Figure 11-8 shows the bits in the PI.
31
Figure 11-8. Processor Initialization Register (PI)
Table 11-9 describes the bit settings for the PI.
Table 11-9. PI Register Field Descriptions—Offset 0x4_1090
Reset
Bits
Name
Value
31–1
—
All 0s
0
P0
0
11.9.6 Spurious Vector Register (SVR)
The spurious vector register contains the 8-bit vector returned to the processor during an
interrupt acknowledge cycle for the cases described in Section 11.3.5, "Spurious Vector
Generation." Note that this register is read/write. Figure 11-9 shows the bits in the SVR.
31
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Processor 0 soft reset
0 Default value
1 Setting this bit causes the EPIC unit to assert the internal sreset signal to the
processor core, causing a soft reset exception. The sreset signal is edge-sensitive to
the processor, but it is held active until a zero is written to P0. Thus, it should be
cleared by software as soon as possible in the soft reset exception handler.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-9. Spurious Vector Register (SVR)
Reserved
Description
8 7
Register Definitions
P0
1 0
Reserved
VECTOR
0
11-19