Memory Control Configuration Register 4 (Mccr4)—0Xfc - Motorola MPC8240 User Manual

Table 4-40. Bit Settings for MCCR3—0xF8 (Continued)
Bits Name
5–3 RCD
2
2–0 RP
1
Figure 4-32 and Table 4-41 show memory control configuration register 4 (MCCR4)
format and bit settings.
BUF_TYPE[0]
WMODE
PRETOACT
ACTOPRE
31 28 27
Figure 4-32. Memory Control Configuration Register 4 (MCCR4)—0xFC
Reset
Value
000 RAS to CAS delay interval. For DRAM/EDO only. These bits control the
number of clock cycles between the assertion of RAS and the first assertion of
CAS. The value for RCD
frequency of the memory interface. However, RCD
cycles. See Section 6.3.5, "FPM or EDO DRAM Interface Timing," for more
information.
001 Reserved
010 2 clocks
011 3 clocks
... ...
111 7 clocks
000 8 clocks
000 RAS precharge interval. For DRAM/EDO only. These bits control the number
of clock cycles that RAS must be held negated (to allow for row precharge)
before the next assertion of RAS. Note that RP
cycles and no greater than 5 clock cycles. See Section 6.3.5, "FPM or EDO
DRAM Interface Timing," for more information.
010 2 clocks
011 3 clocks
110 4 clocks
101 5 clocks
All others: reserved
0
24 23 22 21 20 19 18 17 16 15 14
Chapter 4. Configuration Registers
Memory Control Configuration Registers
Description
depends on the specific DRAMs used and the
2
BUF_TYPE[1]
BSTOPRE[0–1]
REGDIMM
0 0 SDMODE
must be at least two clock
2
must be at least two clock
1
Reserved
BSTOPRE[6–9]
ACTORW
8 7 4 3 0
4-51