Direct And Serial Destination Registers (Idr And Sdr) - Motorola MPC8240 User Manual

Register Definitions
Table 11-22. EUMBBAR Offsets for IDRs and SDRs
IDR
IDR0
IDR1
IDR2
IDR3
IDR4
Figure 11-16 shows the bits of the IDRs and SDRs.
31
Figure 11-16. Direct and Serial Destination Registers (IDR and SDR)
Table 11-23 shows the bit settings for the IDRs and SDRs.
Reset
Bits Name
Value
31–1 — All 0s
0 P0
11.9.8.3 Internal (I
(IIVPRs)
The IIVPRs have the same format and field descriptions as the GTVPRs, except that they
apply to the internal MPC8240 interrupt sources—the I
MU. See Section 11.9.7.4, "Global Timer Vector/Priority Registers (GTVPRs)," for a
complete description of the GTVPRs.
11.9.8.4 Internal (I
(IIDRs)
The IIDRs have the same format and field descriptions as the IDRs (and SDRs), except that
they apply to the internal MPC8240 interrupt sources—the I
channels), and MU. See Section 11.9.8.2, "Direct & Serial Interrupt Destination Registers
(IDRs, SDRs)," for a complete description of the IDRs.
11-26
Offset SDR
0x5_0210 SDR0
0x5_0230 SDR1
0x5_0250 SDR2
0x5_0270 SDR3
0x5_0290 SDR4
SDR5
SDR6
SDR7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 11-23. IDR and SDR Field Descriptions
Reserved
1 Processor 0. Direct and serial interrupts always directed to the processor.
2
C, DMA, MU) Interrupt Vector/Priority Registers
2
C, DMA or MU) Interrupt Destination Registers
MPC8240 Integrated Processor User's Manual
Offset SDR
0x5_0210 SDR8
0x5_0230 SDR9
0x5_0250 SDR10
0x5_0270 SDR11
0x5_0290 SDR12
0x5_02B0 SDR13
0x5_02D0 SDR14
0x5_02F0 SDR15
Reserved
Description
2
C unit, DMA unit (2 channels), and
Offset
0x5_0310
0x5_0330
0x5_0350
0x5_0370
0x5_0390
0x5_03B0
0x5_03D0
0x5_03F0
P0
1 0
2
C unit, DMA unit (2