Rmw Parity Latency Considerations - Motorola MPC8240 User Manual

The MPC8240 checks parity on all memory reads, provided parity checking is enabled
(PCKEN = 1). The MPC8240 generates parity for the following operations:
• PCI to memory write operations
• Processor core single-beat write operations with RMW parity enabled
(RMW_PAR = 1)
The processor core is expected to generate parity for all other memory write operations as
the data goes directly to memory and does not pass through the MPC8240.

6.2.9.1 RMW Parity Latency Considerations

When RMW parity is enabled, the time required to read, modify, and write increases
latency for both processor single-beat writes and PCI writes to system memory. All other
transactions are unaffected and operate as in normal parity mode.
For processor core single-beat writes to system memory, the MPC8240 latches the data,
reads a double word from system memory (checking parity), and then merges that double
word with the write data from the processor. The MPC8240 then generates new parity bits
for the merged double word and writes the data and parity to memory. The
read-modify-write process adds six clock cycles to a single-beat write operation. If page
mode retention is enabled (BSTOPRE > 0 and PGMAX > 0), the MPC8240 keeps the
memory in page mode for the read-modify-write sequence. Because the processor drives
all eight parity bits during burst writes to system memory, these transactions go directly to
the SDRAMs with no performance penalty.
For PCI writes to system memory with RMW parity enabled, the MPC8240 latches the data
in the internal PCI-to-system-memory-write buffer (PCMWB). If the PCI master writes
complete double words to system memory, the MPC8240 generates the parity bits when the
PCMWB is flushed to memory. However, if the PCI master writes 32-, 16-, or 8-bit data
that cannot be gathered into a complete double word in the PCMWB, a read-modify-write
operation is required. The MPC8240 performs a double-word read from system memory
(checking parity), and then merges the write data from the PCI master with the data read
from memory. The MPC8240 then generates new parity for the merged double word and
writes the data and parity to memory. If page mode retention is enabled (BSTOPRE > 0 and
PGMAX > 0), the MPC8240 keeps the memory in page mode for the read-modify-write
sequence.
6.2.10 SDRAM In-Line ECC
As an alternative to simple parity, the MPC8240supports ECC for the data path between the
MPC8240 and system memory. ECC not only allows the MPC8240 to detect errors in the
memory data path but also to correct single-bit errors in the 64-bit data path. Note that ECC
is not supported for systems using a 32-bit data bus. ECC requires a read-modify-write to
perform sub-double word write operations.
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
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