Initialization Options For Pci Controller - Motorola MPC8240 User Manual

Table 7-8. Initialization Options for PCI Controller
Bus Master Mode ROM Location
(MAA1 at Reset) (RCS0 at Reset)
Host Local memory
(MAA1 high) space
(RCS0 high)
Host PCI memory space
(MAA1 high) (RCS0 low)
Agent Local memory
(MAA1 low) space
(RCS0 high)
Agent PCI memory space
(MAA1 low) (RCS0 low)
7.7.2 Accessing the MPC8240 Configuration Space
The MPC8240 responds to PCI configuration accesses from external PCI agents when the
MPC8240's IDSEL input signal is asserted. This allows an external agent access to a subset
of the MPC8240's internal configuration registers. The configuration of the internal
registers of the MPC8240 that are not accessible to external agents is described in
Section 4.1, "Configuration Register Access."
When accessing the MPC8240's configuration registers, the external agent performs the
translation shown in Figure 7-10. The external agent uses the appropriate device number to
assert the MPC8240's IDSEL input; the desired function/register number from 0x00 to
0x47 as described in Section 4.1.3.2, "PCI-Accessible Configuration Registers."
Note that the MPC8240 must not issue PCI configuration transactions to itself (that is, for
PCI configuration transactions initiated by the MPC8240, its IDSEL input signal must not
be asserted).
Initial Settings of PCI Command Register,
PCI command register [2,1] set to
10 Master enabled, target disabled
Boot vector fetch is sent to ROM located on the local memory interface.
PCI command register [2,1] set to
10 Master enabled, target disabled
Boot vector fetch is sent to PCI, and is issued on the bus unaltered.
PCI command register [2,1] set to
00 Master disabled, target disabled
Boot vector fetch is sent to ROM located on the local memory
bus.Processor core configures local memory and has the option to set
bit 10 (RTY_PCI_CFG) of the PCI arbiter control register (PACR) to
force PCI configuration cycles to be retried until local configuration is
complete (see Section 7.7.3, "PCI Configuration Cycle Retry Capability
in Agent Mode"). The MPC8240 can not issue transactions on the PCI
bus until the master enable bit is set.
PCI command register [2,1] set to
00 Master disabled, target disabled
Boot vector fetch is sent to PCI bus where it is not allowed to proceed
until the host CPU enables bus mastership for the MPC8240 in the PCI
control register. The processor core then proceeds sending the boot
vector fetch to the PCI bus unaltered.
Chapter 7. PCI Bus Interface
PCI Host and Agent Modes
and Boot Vector Fetch
7-33