Chaining Of Dma Descriptors In Memory - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Figure 8-3 shows how the DMA descriptors in memory are chained together.
Current Descriptor Address Register
31
Figure 8-3. Chaining of DMA Descriptors in Memory
0
Local Memory or PCI Memory
Offset
Source address
0x00
Reserved
0x04
0x08
Destination address
0x0C
Reserved
Next descriptor
0x10
Reserved
0x14
0x18
Byte count
Reserved
0x1C
31
Offset
Source address
0x00
0x04
Reserved
0x08
Destination address
0x0C
Reserved
Next descriptor
0x10
Reserved
0x14
Byte count
0x18
Reserved
0x1C
31
Offset
Source address
0x00
0x04
Reserved
0x08
Destination address
0x0C
Reserved
Next descriptor
0x10
0x14
Reserved
Byte count
0x18
Reserved
0x1C
31
Chapter 8. DMA Controller
DMA Descriptors for Chaining Mode
Descriptor 0
0
Descriptor 1
Control fields as
described in Table 8-4
0
Descriptor n
0
8-13

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