Motorola MPC8240 User Manual page 635

Processor bus error status registers, 13-6
Processor control instructions, D-24
Processor core
block diagram, 5-2
cache implementation, 5-20
cache units, 5-9
description, 5-1
differences with the MPC8240, 5-34
dispatch unit, 5-6
execution units, 5-6
features list, 5-3
floating-point unit, 5-7
instruction queue, 5-6
instruction timing, 5-32
instruction unit, 5-5
integer unit, 5-7
memory management unit, 5-8, 5-30
overview, 1-7, 5-1
programming model, 5-10
Processor interface
bus error signals, 13-3
byte ordering, B-1
configuration registers, 4-29
error detection, 13-6
local memory buffer, 12-3
PCI buffers, 12-4
processor bus error status register, 13-6
programmable parameters
parking, 4-29
PICR1/PICR2 registers, 4-29
registers, see Registers, processor interface
shared data bus, 12-2
unsupported bus transactions error, 13-6
Programmable power states
doze mode, 14-4
full-power mode (DPM enabled/disabled), 14-4
nap mode, 14-5
sleep mode, 14-6
PVR (processor version register), 5-17, E-15, E-15
Q
QACK (quiesce acknowledge) signal, 2-28
QBAR (queue base address) register, 9-21
R
RAM access time, 4-46
RASn (row address strobe) signals, 2-16
RCSn (ROM bank select) signals, 2-22
Registers
accessing registers, 4-2–4-5
CONFIG_ADDR register, 7-24
CONFIG_DATA register, 7-24
address translation registers, 3-14
INDEX
ITWR, 3-15
LMBAR, 3-15
OMBAR, 3-16
OTWR, 3-17
configuration header summary, 4-10, 7-22
configuration registers
error handling registers, 2-27, 13-4
60x/PCI error address register, 4-40
BESR, 4-34, 4-37
ECC single-bit error registers, 4-33
ErrDRs, 4-36, 13-5
ErrEnRs, 4-35
PCI bus error status register, 4-40, 7-30
processor bus error status register, 4-40, 13-6
memory interface
MCCRn, 4-42–4-54
memory bank enable register, 4-27
memory boundary registers, 4-23
memory page mode register, 4-28
MSR, E-13
PCI interface
command register, 4-11, 4-11, 7-22
ILR, 4-16
LMBAR, 4-15
optional register, BIST control, 4-10
PACR, 4-16
PBCCR, 4-14
PCLSR, 4-14
PCSRBAR, 4-15
PIR, 4-14
PLTR, 4-14
register summary, 4-10
status register, 4-12, 7-22–7-31
VPICR, 4-29
power management
PMCRn, 4-17–4-19
processor interface
PICRs, 4-29–4-33
PVR, E-12, E-15
DCMP, 5-13, E-20
debug registers
DH error capture monitor register, 15-19
DH error injection mask register, 15-17
DL error capture monitor register, 15-20
parity error capture monitor register, 15-20
DMA registers
BCR, 8-21
CDAR, 8-19
DAR, 8-21
DMR, 8-15
DSR, 8-18
NDAR, 8-23
SAR, 8-20
DMISS, 5-13, E-20
doorbell registers, 1-15
Index Index-11