Reset Status Register - Motorola MPC823e Reference Manual

4.2 RESET STATUS REGISTER

The 32-bit reset status register (RSR) is powered by the keep-alive power supply. As shown
in Section 3 Memory Map , it is memory-mapped into the MPC823e system interface unit
register map and receives its default reset values at power-on reset.
RSR
BIT 0 1 2
FIELD
EHRS ESRS LLRS
RESET
1 1 0
R/W
R/W R/W R/W
BIT 16 17 18
FIELD
RESET
R/W
EHRS—External Hard Reset Status
This bit is cleared by a power-on reset. When an external hard reset event is detected, this
bit is set and remains that way until the software clears it. The EHRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No external hard reset event occurred.
1 = An external hard reset event occurred.
ESRS—External Soft Reset Status
This bit is cleared by a power-on reset. When an external soft reset event is detected, this
bit is set and remains that way until the software clears it. The ESRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No external soft reset event occurred.
1 = An external soft reset event occurred.
LLRS—Loss-of-Lock Reset Status
This bit is cleared by a power-on reset. When a loss-of-lock event is enabled by the LOLRE
bit in the PLPRCR is detected, this bit is set and remains that way until the software clears
it. The LLRS bit can be negated by writing a 1, but a write of zero has no effect on it.
0 = No enabled loss-of-lock reset event occurred.
1 = An enabled loss-of-lock reset event occurred.
MOTOROLA
3 4 5 6 7
SWRS CSRS DBHRS DBSRS JTRS
0 0 0 0 0
R/W R/W R/W R/W R/W
19 20 21 22 23
RESERVED
0
R/W
MPC823e REFERENCE MANUAL
8 9 10 11 12
RESERVED
0
R/W
24 25 26 27 28
Reset
13 14 15
29 30 31
4-5