Dmr Field Descriptions—Offsets 0X100, 0X200 - Motorola MPC8240 User Manual

DMA Register Descriptions
Table 8-3 describes the bit settings for the DMRs.
Table 8-3. DMR Field Descriptions—Offsets 0x100, 0x200
Reset
Bits Name
Value
31–22 — 0
21–20 LMDC 00
19 IRQS 0
18 PDE 0
17–16 DAHTS 00
15–14 SAHTS 00
13 DAHE 0
12 SAHE 0
8-16
R/W
R Reserved
RW Local memory delay count. This field controls the delay between the DMA transfer
of each cache line (32 bytes) access to local memory. The delay value is the time
from the last successful DMA transfer until the next request occurs to local
memory. Increasing this value to something greater than 0b00 gives a greater
probability of PCI accesses gaining arbitration to the shared processor/memory
bus while a DMA transfer is in progress. Refer to Section 12.2.1, "Arbitration
Between PCI and DMA Accesses to Local Memory," for more information.
00 4 sys_logic_clk cycles
01 8 sys_logic_clk cycles
10 16 sys_logic_clk cycles
11 32 sys_logic_clk cycles
RW Interrupt steer
0 Routes all DMA interrupts to the processor core through the internal int
mechanism and the EPIC unit.
1 Routes all DMA interrupts to the PCI bus through the external INTA signal.
RW Periodic DMA enable. Applies only to chaining mode. Otherwise, it is ignored.
Refer to Section 8.3.2.2, "Periodic DMA Feature," for more information.
0 Disables periodic DMA restart
1 Allows hardware to periodically restart the DMA process.
RW Destination address hold transfer size. Applies only to direct mode (not used in
chaining mode). Indicates the transfer size used for each transaction when the
DAHE bit is set. The BCR value must be in multiples of this size and the DAR
value must be aligned based on this size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
RW Source address hold transfer size. Applies only to direct mode (not used in
chaining mode). Indicates the transfer size used for each transaction when the
SAHE bit is set.The BCR value must be in multiples of this size and the SAR
value must be aligned based on this size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
RW Destination address hold enable (direct mode only). Applies only to direct mode
(not used in chaining mode). Allows the DMA controller to hold the destination
address to a fixed value for every transfer. The size used for the transfers is
indicated by DAHTS. The MPC8240 only supports aligned transfers for this
feature. Only one of DAHE or SAHE may be set at one time.
0 Disables the destination address hold feature
1 Enables the destination address hold feature
RW Source address hold enable (direct mode only). Applies only to direct mode (not
used in chaining mode). Allows the DMA controller to hold the source address to
a fixed value for every transfer. The size used for the transfers is indicated by
SAHTS. The MPC8240 only supports aligned transfers for this feature. Only one
of DAHE or SAHE may be set at one time.
0 Disables the source address hold feature
1 Enables the source address hold feature
MPC8240 Integrated Processor User's Manual
Description