Motorola MPC8240 User Manual page 633

MPC8240
differences with the processor core, 5-34
implementation-specific registers, 5-13, E-20
MMU features, 5-31
peripheral logic block diagram, 1-11
possible applications, 1-5
processor core block diagram, 5-2
processor core differences, 5-34
uses for the MPC8240, 1-5
MSR (machine state register)
FE0/FE1 bits, E-15
MUCR (messaging unit control) register, 9-20
Munging
definition, B-1
munged little endian mode, see also PowerPC lit-
tle-endian (PPC-LE) mode
munged memory image, LE mode, B-7
N
Nap mode
description, 14-9
overview, 1-18
NDAR (next descriptor address) register, 8-23
NMI (nonmaskable interrupt)
signal, 2-27, 13-5, 13-11
O
ODCR (output driver control) register, 4-20
OEA (operating environment architecture)
register set, E-11
OFHPR (outbound free_FIFO head pointer)
register, 9-18
OFQPR (outbound FIFO queue port) register, 9-12
OFTPR (outbound free_FIFO tail pointer)
register, 9-18
OMBAR (outbound memory base address)
register, 3-16
OMIMR (outbound message interrupt mask)
register, 9-10
OMISR (outbound message interrupt status)
register, 9-9
Operands
BO operand encodings, E-9
OPHPR (outbound post_FIFO head pointer)
register, 9-19
Optional instructions, D-38
OPTPR (outbound post_FIFO tail pointer)
register, 9-19
OSC_IN (system clock input) signal, 2-33
OTWR (outbound translation window) register, 3-17
Overview
MPC8240, 1-1
processor core, 1-7, 5-1
INDEX
P
PAR (PCI parity) signal, 2-10, 7-31
Parity
SDRAM interface
parity, 6-26
read-modify-write (RMW) parity, 6-26
Parity error capture monitor register, 15-20
Parity error injection mask register, 15-18
PARn (data parity/ECC) signals, 2-20
PBCCR (PCI base class code) register, 4-14
PCI interface
accessing registers, see Registers, 7-24
address bus decoding, 7-11
address map A
direct-access PCI configuration, A-6
overview, 3-1
PCI I/O master view, A-2
address map B
overview, 3-1
PCI I/O master view, 3-3
PCI memory master view in agent mode, 3-3
processor view in host mode, 3-2, 3-8
address translation, 7-34
address/data parity errors, 7-19, 13-9
big-endian mode, four-byte transfer, B-3
burst operation, 7-9
bus arbitration, 1-14, 7-4
bus commands, 7-9
bus error signals, 13-4
bus protocol, 7-8
bus transactions
interrupt-acknowledge transaction, 7-27
read transactions, 7-14
special-cycle transaction, 7-28
timing diagrams, 7-14
transaction termination, 7-17
write transactions, 7-16
byte alignment, 7-13, B-2
byte ordering, 7-2, B-1
C/BE signals, 7-31
cache wrap mode, 7-12
configuration cycles
configuration header, 7-22
direct access method, 7-26
type 0 and 1 accesses, 7-23
configuration space addressing, 7-12
data transfers, 7-9
error detection and reporting, 7-30, 13-4, 13-9
error transactions, 7-30
exclusive access, 7-29
fast back-to-back transactions, 7-21
features list, 1-12
I/O space addressing, 7-12
linear incrementing, 7-12
Index Index-9