Table Of Contents - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
Table of Contents

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Paragraph
Number
1.1
MPC8240 Integrated Processor Overview.......................................................... 1-1
1.1.1
MPC8240 Integrated Processor Features........................................................ 1-3
1.1.2
MPC8240 Integrated Processor Applications................................................. 1-5
1.2
Processor Core Overview ................................................................................... 1-7
1.3
Peripheral Logic Bus......................................................................................... 1-10
1.4
Peripheral Logic Overview ............................................................................... 1-11
1.4.1
Peripheral Logic Features ............................................................................. 1-11
1.4.2
Peripheral Logic Functional Units................................................................ 1-12
1.4.3
Memory System Interface............................................................................. 1-13
1.4.4
Peripheral Component Interconnect (PCI) Interface .................................... 1-14
1.4.4.1
PCI Bus Arbitration Unit .......................................................................... 1-14
1.4.4.2
Address Maps and Translation ................................................................. 1-14
1.4.4.3
Byte Ordering ........................................................................................... 1-15
1.4.4.4
PCI Agent Capability................................................................................ 1-15
1.4.5
DMA Controller............................................................................................ 1-15
1.4.6
Message Unit (MU) ...................................................................................... 1-15
1.4.6.1
Doorbell Registers .................................................................................... 1-15
1.4.6.2
Inbound and Outbound Message Registers .............................................. 1-16
1.4.6.3
1.4.7
1.4.8
Embedded Programmable Interrupt Controller (EPIC) ................................ 1-16
1.4.9
Integrated PCI Bus and SDRAM Clock Generation .................................... 1-17
1.5
Power Management .......................................................................................... 1-18
1.5.1
Programmable Processor Power Management Modes ................................. 1-18
1.5.2
1.6
Programmable I/O Signals with Watchpoint .................................................... 1-19
1.7
Debug Features ................................................................................................. 1-19
1.7.1
Memory Attribute and PCI Attribute Signals ............................................... 1-20
1.7.2
Memory Debug Address............................................................................... 1-20
1.7.3
Memory Interface Valid (MIV) .................................................................... 1-20
CONTENTS
Title
Chapter 1
O) ................................................. 1-16
2
2
C) Controller....................................................... 1-16
Contents
Page
Number
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