Paragraph
Number
1.1
1.1.1
1.1.2
1.2
1.3
Peripheral Logic Bus......................................................................................... 1-10
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.4.1
1.4.4.2
1.4.4.3
Byte Ordering ........................................................................................... 1-15
1.4.4.4
PCI Agent Capability................................................................................ 1-15
1.4.5
DMA Controller............................................................................................ 1-15
1.4.6
Message Unit (MU) ...................................................................................... 1-15
1.4.6.1
Doorbell Registers .................................................................................... 1-15
1.4.6.2
1.4.6.3
1.4.7
1.4.8
1.4.9
1.5
Power Management .......................................................................................... 1-18
1.5.1
1.5.2
1.6
1.7
Debug Features ................................................................................................. 1-19
1.7.1
1.7.2
Memory Debug Address............................................................................... 1-20
1.7.3
CONTENTS
Title
Chapter 1
O) ................................................. 1-16
2
2
C) Controller....................................................... 1-16
Contents
Page
Number
v