Motorola MPC8240 User Manual page 16

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9.3.4.2.6
9.3.4.2.7
9.3.4.2.8
9.3.4.2.9
9.3.4.2.10
9.3.4.2.11
9.3.4.2.12
2
10.1 I C Interface Overview ..................................................................................... 10-1
2
10.1.1 I C Unit Features .......................................................................................... 10-1
2
10.1.2 I C Interface Signal Summary...................................................................... 10-2
2
10.1.3 I C Register Summary .................................................................................. 10-2
2
10.1.4 I C Block Diagram ....................................................................................... 10-3
2
10.2 I C Protocol ...................................................................................................... 10-3
10.2.1 START Condition......................................................................................... 10-4
10.2.2 Slave Address Transmission......................................................................... 10-4
10.2.3 Data Transfer ................................................................................................ 10-5
10.2.4 Repeated START Condition......................................................................... 10-5
10.2.5 STOP Condition............................................................................................ 10-5
10.2.6 Arbitration Procedure ................................................................................... 10-5
10.2.7 Clock Synchronization.................................................................................. 10-6
10.2.8 Handshaking ................................................................................................. 10-7
10.2.9 Clock Stretching ........................................................................................... 10-7
2
10.3 I C Register Descriptions ................................................................................. 10-7
2
10.3.1 I C Address Register (I2CADR) .................................................................. 10-7
2
10.3.2 I C Frequency Divider Register (I2CFDR) .................................................. 10-8
2
10.3.3 I C Control Register (I2CCR) .................................................................... 10-10
2
10.3.4 I C Status Register (I2CSR) ....................................................................... 10-11
2
10.3.5 I C Data Register (I2CDR)......................................................................... 10-13
10.4 Programming Guidelines ................................................................................ 10-13
10.4.1 Initialization Sequence................................................................................ 10-14
10.4.2 Generation of START................................................................................. 10-14
10.4.3 Post-Transfer Software Response............................................................... 10-14
10.4.4 Generation of STOP.................................................................................... 10-15
10.4.5 Generation of Repeated START................................................................. 10-15
10.4.6 Generation of SCK when SDA Low........................................................... 10-15
10.4.7 Slave Mode Interrupt Service Routine........................................................ 10-16
10.4.7.1 Slave Transmitter and Received Acknowledge ...................................... 10-16
10.4.7.2 Loss of Arbitration and Forcing of Slave Mode ..................................... 10-16
10.4.8 Interrupt Service Routine Flowchart........................................................... 10-16
xvi
CONTENTS
Inbound Post_FIFO Tail Pointer Register (IPTPR) ............................. 9-17
Outbound Free_FIFO Head Pointer Register (OFHPR)....................... 9-18
Outbound Free_FIFO Tail Pointer Register (OFTPR) ......................... 9-18
Outbound Post_FIFO Head Pointer Register (OPHPR)....................... 9-19
Outbound Post_FIFO Tail Pointer Register (OPTPR) ......................... 9-19
Messaging Unit Control Register (MUCR).......................................... 9-20
Queue Base Address Register (QBAR)................................................ 9-21
Chapter 10
2
I C Interface
MPC8240 Integrated Processor User's Manual
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