Motorola MPC8240 User Manual page 405

Table 10-6. I2CCR Field Descriptions—Offset 0x0_3008 (Continued)
Reset
Bits Name
Value
3 TXAK 0
2 RSTA 0
1–0 — 00
2
10.3.4 I C Status Register (I2CSR)
The status register, shown in Figure 10-6, is read-only with the exception of the MIF and
MAL bits, which can be cleared by software. The MCF and RXAK bits are set at reset; all
other I2CSR bits are cleared on reset.
31
R/W
R/W Transfer acknowledge. This bit specifies the value driven onto the SDA line during
acknowledge cycles for both master and slave receivers. The value of this bit
applies only when the I
does not apply to address cycles; when the MPC8240 is addressed as a slave, an
acknowledge is always sent.
0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock
bit after receiving one byte of data.
1 No acknowledge signal response is sent (that is, acknowledge value on SDA is
high).
W Repeat START. Setting this bit causes a repeated START condition to be always
generated on the bus, provided the MPC8240 is the current bus master. Attempting
a repeated START at the wrong time (or if the bus is owned by another master)
results in loss of arbitration. Note that this bit is not readable.
0 No repeat START condition
1 Generates repeat START condition
R Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
Figure 10-6. I C Status Register (I2CSR)
Chapter 10. I
Description
2
C module is configured as a receiver, not a transmitter and
RXAK
MIF
SRW
MAL
MBB
MAAS
MCF
2
C Interface
2
I C Register Descriptions
Reserved
0
8 7 6 5 4 3 2 1 0
10-11