Error Enabling Register 1 (Errenr1)—0Xc0 - Motorola MPC8240 User Manual

Memory Refresh Overflow Enable
Memory Select Error Enable
PCI Target PERR Enable
RX_SERR_EN
Figure 4-21. Error Enabling Register 1 (ErrEnR1)—0xC0
Table 4-30. Bit Settings for Error Enabling Register 1 (ErrEnR1)—0xC0
Bits Name
7 RX_SERR_EN
6 PCI target PERR
enable
5 Memory select error
enable
4 Memory refresh
overflow enable
3 PCI master PERR
enable
2 Memory parity/ECC
enable
7 6 5 4
Reset
Value
0 This bit enables the reporting of SERR assertions that occur on the PCI
bus two clock cycles after the address phase of transactions where the
MPC8240 is the initiator.
0 Received PCI SERR disabled
1 Received PCI SERR enabled
0 This bit enables the reporting of data parity errors on the PCI bus for
transactions involving the MPC8240 as a target.
0 Target PERR disabled
1 Target PERR enabled
0 This bit enables the reporting of memory select errors that occur on
(attempted) accesses to system memory.
0 Memory select error disabled
1 Memory select error enabled
0 This bit enables the reporting of memory refresh overflow errors.
0 Memory refresh overflow disabled
1 Memory refresh overflow enabled
0 This bit enables the reporting of data parity errors on the PCI bus for
transactions involving the MPC8240 as a master.
0 Master PERR disabled
1 Master PERR enabled
0 This bit enables the reporting of system memory read parity errors that
occur on accesses to system memory or those that exceed the ECC
single-bit error threshold. [For SDRAM with in-line ECC/parity, this is the
memory write parity enable bit.]
0 Memory read parity/ECC single-bit threshold disabled
1 Memory read parity/ECC single-bit threshold enabled
Chapter 4. Configuration Registers
Error Handling Registers
PCI Master PERR Enable
Memory Parity/ECC Enable
PCI Master-Abort Error Enable
Processor Transaction Error Enable
3 2 1 0
Description
4-35