Error Detection Register 1 (Errdr1)—0Xc1 - Motorola MPC8240 User Manual

Error Handling Registers
Table 4-30. Bit Settings for Error Enabling Register 1 (ErrEnR1)—0xC0 (Continued)
Bits Name
1 PCI master-abort
error enable
0 Processor transaction
error enable
Figure 4-22 shows the bits of error detection register 1.
Memory Refresh Overflow Error
Memory Select Error
PCI Target PERR
PCI SERR
Figure 4-22. Error Detection Register 1 (ErrDR1)—0xC1
Table 4-31 describes the bits of error detection register 1.
Table 4-31. Bit Settings for Error Detection Register 1 (ErrDR1)—0xC1
Bits Name
7 PCI SERR
6 PCI target PERR
5 Memory select error
4 Memory refresh
overflow error
3 Processor/PCI cycle
4-36
Reset
Value
0 This bit enables the reporting of master-abort errors that occur on the PCI
bus for transactions involving the MPC8240 as a master.
0 PCI master-abort error disabled
1 PCI master-abort error enabled
1 This bit enables the reporting of processor transaction errors.
0 Processor transaction error disabled
1 Processor transaction bus error enabled
7 6 5
Reset
Value
0 MPC8240, as a PCI initiator, detected SERR asserted by an external PCI
agent two clock cycles after the address phase.
0 SERR not detected
1 SERR detected
0 PCI target PERR
0 The MPC8240, as a PCI target, has not detected a data parity error
1 The MPC8240, as a PCI target, detected a data parity error
0 Memory select error
0 No error detected
1 Memory select error detected
0 Memory refresh overflow error
0 No error detected
1 Memory refresh overflow has occurred
0 Processor/PCI cycle
0 Error occurred on a processor-initiated cycle.
1 Error occurred on a PCI-initiated cycle.
MPC8240 Integrated Processor User's Manual
Description
Processor/PCI Cycle
Memory Read Parity Error/
ECC Single-Bit Error Exceeded
Unsupported Processor
Transaction
4 3 2 1˙ 0
Description