Motorola MPC8240 User Manual page 9

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3.1 Address Map B ................................................................................................... 3-1
3.2 Address Map B Options...................................................................................... 3-7
3.2.1 Processor Compatibility Hole and Alias Space .............................................. 3-7
3.2.2 PCI Compatibility Hole and Alias Space ....................................................... 3-9
3.3 Address Translation .......................................................................................... 3-11
3.3.1 Inbound PCI Address Translation................................................................. 3-11
3.3.2 Outbound PCI Address Translation.............................................................. 3-13
3.3.3 Address Translation Registers ...................................................................... 3-14
3.3.3.1 Local Memory Base Address Register (LMBAR) ................................... 3-15
3.3.3.2 Inbound Translation Window Register (ITWR)....................................... 3-15
3.3.3.3 Outbound Memory Base Address Register (OMBAR) ............................ 3-16
3.3.3.4 Outbound Translation Window Register (OTWR)................................... 3-17
3.4 Embedded Utilities Memory Block (EUMB) ................................................... 3-18
3.4.1 Processor Core Control and Status Registers ............................................... 3-18
3.4.2 Peripheral Control and Status Registers ....................................................... 3-19
4.1 Configuration Register Access ........................................................................... 4-1
4.1.1 Configuration Register Access in Little-Endian Mode................................... 4-2
4.1.2 Configuration Register Access in Big-Endian Mode ..................................... 4-3
4.1.3 Configuration Register Summary ................................................................... 4-5
4.1.3.1 Processor-Accessible Configuration Registers........................................... 4-5
4.1.3.2 PCI-Accessible Configuration Registers .................................................... 4-8
4.2 PCI Interface Configuration Registers.............................................................. 4-10
4.2.1 PCI Command Register-Offset 0x04 ......................................................... 4-11
4.2.2 PCI Status Register-Offset 0x06 ................................................................ 4-12
4.2.3 Programming Interface-Offset 0x09 .......................................................... 4-14
4.2.4 PCI Base Class Code-Offset 0x0B............................................................. 4-14
4.2.5 PCI Cache Line Size-Offset 0x0C ............................................................. 4-14
4.2.6 Latency Timer-Offset 0x0D....................................................................... 4-14
4.2.7 PCI Base Address Registers-LMBAR and PCSRBAR ............................. 4-15
4.2.8 PCI Interrupt Line-Offset 0x3C ................................................................. 4-16
4.2.9 PCI Arbiter Control Register (PACR)-Offset 0x46 ................................... 4-16
4.3 Peripheral Logic Power Management Configuration Registers (PMCRs) ....... 4-17
4.3.1 Power Management Configuration Register 1 (PMCR1)-Offset 0x70...... 4-17
4.3.2 Power Management Configuration Register 2 (PMCR2)-Offset 0x72...... 4-18
4.4 Output/Clock Driver and Miscellaneous I/O Control Registers ....................... 4-20
CONTENTS
Title
Chapter 3
Address Maps
Chapter 4
Configuration Registers
Contents
Page
Number
ix