Epic Unit Interrupt Protocol - Motorola MPC8240 User Manual

Table 11-3. EPIC Register Address Map—Interrupt Source
Address Offset
from EUMBBAR
0x5_10D0 Message unit interrupt destination register (IIDR3)
0x5_10E0–0x5_FFF0 Reserved
Table 11-4. EPIC Register Address Map—Processor-Related Registers
Address Offset
from EUMBBAR
0x6_0000–0x6_0070
0x6_0080
0x6_0090
0x6_00A0
0x6_00B0
0x6_00C0–0x6_3FF0

11.3 EPIC Unit Interrupt Protocol

The following sections describe the priority of interrupts controlled by the EPIC unit, the
interrupt acknowledge mechanism, the nesting of multiple interrupts, and the handling of
spurious interrupts.
11.3.1 Interrupt Source Priority
The software assigns a priority value to each interrupt source by writing to the
vector/priority register for the particular source. Priority values are in the range 0 to 15 of
which 15 is the highest. In order for an interrupt to be signalled to the processor, the priority
of the source must be greater than that of the current task priority of the processor (and the
in-service interrupt source priority). Therefore, setting a source priority to zero inhibits that
interrupt.
The EPIC unit services simultaneous interrupts occurring with the same priority according
to the following set order: timer 0–timer 3, DMA 0, DMA 1, MU, I
from IRQ[0:4] (or serial interrupt source).
11.3.2 Processor Current Task Priority
The EPIC unit has a processor current task priority register (PCTPR) set by system software
to indicate the relative importance of the task running on the processor. When an interrupt
has a priority level greater than the current task priority (and the in-service interrupt source
priority), it is signalled to the processor. Therefore, setting the task priority to 15 in the
PCTPR prevents the signalling of any interrupt to the processor.
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
Configuration Registers (Continued)
Register Name
Register Name
Reserved
Processor current task priority register (PCTPR)
Reserved
Processor interrupt acknowledge register (IACK)
Processor end-of-interrupt register (EOI)
Reserved
EPIC Unit Interrupt Protocol
Field Mnemonics
P0
—
Field Mnemonics
—
TASKP
—
VECTOR
EOI_CODE
—
2
C, direct interrupts
11-7