Motorola MPC8240 User Manual page 616

MPC8240-Specific Registers
Table E-20. HID0 Field Descriptions (Continued)
Bits Name
18 ILOCK Instruction cache lock
0 Normal operation
1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is
treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is
single-beat.
To prevent locking during a cache access, an isync must precede the setting of ILOCK.
19 DLOCK Data cache lock
0 Normal operation
1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated
as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is
single-beat.
A snoop hit to a locked L1 data cache performs as if the cache were not locked. A cache block
invalidated by a snoop remains invalid until the cache is unlocked.
To prevent locking during a cache access, a sync must precede the setting of DLOCK.
20 ICFI Instruction cache flash invalidate
0 The instruction cache is not invalidated. The bit is cleared when the invalidation operation
begins (usually the next cycle after the write operation to the register). The instruction cache
must be enabled for the invalidation to occur.
1 An invalidate operation is issued that marks the state of each instruction cache block as
invalid without writing back modified cache blocks to memory. Cache access is blocked during
this time. Accesses to the cache from the peripheral logic bus are signaled as a miss during
invalidate-all operations. Setting ICFI clears all the valid bits of the blocks and the PLRU bits
to point to way L0 of each set. Once this flash invalidate bit is set through an mtspr
instruction, hardware automatically resets this bit in the next cycle (provided that the
corresponding cache enable bit is set in HID0).
21 DCFI Data cache flash invalidate
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins
(usually the next cycle after the write operation to the register). The data cache must be
enabled for the invalidation to occur.
1 An invalidate operation is issued that marks the state of each data cache block as invalid
without writing back modified cache blocks to memory. Cache access is blocked during this
time. Accesses to the cache from the peripheral logic bus are signaled as a miss during
invalidate-all operations. Setting DCFI clears all the valid bits of the blocks and the PLRU bits
so that they point to way L0 of each set. Once the flash invalidate bit is set through an mtspr
instruction, hardware automatically resets this bit in the next cycle (provided that the
corresponding cache enable bit is set in HID0).
22–23 — Reserved
24 — IFEM bit on some other PowerPC devices
This bit is not used in the MPC8240 (and so it is reserved).
25–26 — Reserved
27 FBIOB Force branch indirect on bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally.
28 — Reserved—Used as address broadcast enable bit on some other PowerPC devices
29–30 — Reserved
31 NOOPTI No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled.
1 The dcbt and dcbtst instructions are no-oped globally.
1
See Chapter 9, "Power Management," of the MPC603e User's Manual for more information.
2
See Chapter 3, "Instruction and Data Cache Operation," of the MPC603e User's Manual for more information.
E-26
2
2
MPC8240 Integrated Processor User's Manual
Description