Motorola MPC8240 User Manual page 478

Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes
execute in program order despite the address munging that causes little endian addressing
of instructions already in the cache. If the processor is operating in big-endian mode, these
no-op instructions are not needed.
*********************************************************************
# First set up peripheral logic power management register
# and the processor core HID0 power management bits
#*********************************************************************
#*********************************************************************
# turn on power management bits
#
addis
ori
stwbrx
sync
lhbrx
addis
ori
or
sync
sthbrx
CONFIG_DATA
sync
#******processor HID and external interrupt initialization*******************
#
# set up HID registers for the various PowerPC processors
# hid setup taken from minix's mpxPowerPC.s
mfspr r31, pvr
srawi r31, r31, 16
resetTest603:
cmpi 0, 0, r31, 3
bne cr0, endHIDSetup
addi r0, r0, 0
oris r0, r0, 0x1000
oris r0, r0, 0x0010
oris r0, r0, 0x0020
ori r0, r0, 0x8000
ori r0, r0, 0x4000
ori r0, r0, 0x0800
ori r0, r0, 0x0400
mtspr hid0, r0
isync
#******************************************************************
# then when the processor is in a loop, force an SMI interrupt
#******************************************************************
.orig 0x00001400
# force big endian mode
stw
#code read and execute in program order (up until the isync).
stw
mfmsr
ori
ori
ori
xori
ori
14-12
r3, r0, 0x8000
r3, r3, 0x0070
r3, r0, r1
r4, r0, r2
r0, r0, 0x0000
r0, r0, 0xc088
r4, r4, r0
r4, r0, r2
# pvr reg
# enable machine check pin EMCP
# enable dynamic power mgmt DPM
# enable SLEEP power mode
# enable the Icache ICE
# enable the Dcache DCE
# invalidate Icache ICFI
# invalidate Dcache DCFI
r0,0x05f8,r0
r0,0x05fc,r0
r0
r0,r0,r0
r0,r0,0x0001
r0,r0,r0
r0,r0,0x0001
r0,r0,r0
MPC8240 Integrated Processor User's Manual
# start building new register number
# register number 0xf0
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
# PM=1
# set bits 15, 14, and 7, 3(sleep)
# set the PM bit
# write the
# System management interrupt
# need nop every second inst to make
# force big endian LE bit
# force big endian LE bit
modified data to