Motorola MPC8240 User Manual page 19

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13.3 Error Reporting ................................................................................................. 13-5
13.3.1 Processor Interface Errors............................................................................. 13-6
13.3.1.1 Processor Transaction Error ..................................................................... 13-6
13.3.1.2 Flash Write Error ...................................................................................... 13-7
13.3.1.3 Processor Write Parity Error..................................................................... 13-7
13.3.2 Memory Interface Errors .............................................................................. 13-7
13.3.2.1 Memory Read Data Parity Error............................................................... 13-8
13.3.2.2 Memory ECC Error .................................................................................. 13-8
13.3.2.3 Memory Select Error ................................................................................ 13-9
13.3.2.4 Memory Refresh Overflow Error ............................................................. 13-9
13.3.3 PCI Interface Errors ...................................................................................... 13-9
13.3.3.1 PCI Address Parity Error .......................................................................... 13-9
13.3.3.2 PCI Data Parity Error.............................................................................. 13-10
13.3.3.3 PCI Master-Abort Transaction Termination........................................... 13-10
13.3.3.4 Received PCI Target-Abort Error........................................................... 13-10
13.3.3.5 NMI (Nonmaskable Interrupt) ................................................................ 13-11
13.3.4 Message Unit Error Events ......................................................................... 13-11
13.4 Exception Latencies ........................................................................................ 13-11
14.1 Overview........................................................................................................... 14-1
14.2 Processor Core Power Management ................................................................. 14-1
14.2.1 Dynamic Power Management....................................................................... 14-2
14.2.2 Programmable Power Modes on Processor Core ......................................... 14-2
14.2.3 Processor Power Management Modes-Details........................................... 14-4
14.2.3.1 Full-Power Mode with DPM Disabled ..................................................... 14-4
14.2.3.2 Full-Power Mode with DPM Enabled ...................................................... 14-4
14.2.3.3 Processor Doze Mode ............................................................................... 14-4
14.2.3.4 Processor Nap Mode................................................................................. 14-5
14.2.3.5 Processor Sleep Mode............................................................................... 14-6
14.2.4 Power Management Software Considerations.............................................. 14-6
14.3 Peripheral Logic Power Management............................................................... 14-7
14.3.1 MPC8240 Peripheral Power Mode Transitions ............................................ 14-7
14.3.2 Peripheral Power Management Modes ......................................................... 14-9
14.3.2.1 Peripheral Logic Full Power Mode........................................................... 14-9
14.3.2.2 Peripheral Logic Doze Mode.................................................................... 14-9
14.3.2.3 Peripheral Logic Nap Mode...................................................................... 14-9
14.3.2.3.1
14.3.2.3.2
14.3.2.4 Peripheral Logic Sleep Mode ................................................................. 14-10
CONTENTS
Chapter 14
Power Management
PCI Transactions During Nap Mode .................................................. 14-10
PLL Operation During Nap Mode...................................................... 14-10
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