Processor/Pci Buffers - Motorola MPC8240 User Manual

Processor Address/Control
Processor/ A
Memory
Transaction
Address Buffer
In the case of a snoop for a PCI read from local memory that causes an L1 copyback, the
copyback data is simultaneously latched in the copyback buffer and the
PCI-read-from-local-memory buffer (PCMRB). When the L1 copyback is complete, the
data is forwarded to the PCI agent from the PCMRB. The MPC8240 flushes the data in the
copyback buffer to local memory at the earliest available opportunity.
For processor burst writes to memory with ECC enabled, the MPC8240 uses the copyback
buffer as a temporary holding area while it generates the appropriate ECC codes to send to
memory.
After the copyback buffer has been filled, the data remains in the buffer until the local
memory bus is available to flush the copyback buffer contents to local memory. During the
time that modified data waits in the copyback buffer, all transactions to local memory space
are snooped against the copyback buffer. All PCI-initiated transactions that hit in the
copyback buffer cause the copyback buffer to have the highest priority for being flushed out
to main memory.

12.1.2 Processor/PCI Buffers

There are three data buffers for processor accesses to PCI—one 32-byte
processor-to-PCI-read buffer (PRPRB) for processor reads from PCI, and two 16-byte
processor-to-PCI-write data buffers (PRPWBs) for processor writes to PCI.
Copyback A
Buffer
Figure 12-2. Processor/Local Memory Buffers
Chapter 12. Central Control Unit
Processor/Memory Data
D0 D1 D2 D3
Memory Row/Column Address
Internal Buffers
12-3