Motorola MPC8240 User Manual page 15

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8.6.1 Descriptors in Big-Endian Mode .................................................................. 8-14
8.6.2 Descriptors in Little-Endian Mode ............................................................... 8-14
8.7 DMA Register Descriptions.............................................................................. 8-15
8.7.1 DMA Mode Registers (DMRs)..................................................................... 8-15
8.7.2 DMA Status Registers (DSRs) ..................................................................... 8-18
8.7.3 Current Descriptor Address Registers (CDARs) .......................................... 8-19
8.7.4 Source Address Registers (SARs) ................................................................ 8-20
8.7.5 Destination Address Registers (DARs) ........................................................ 8-21
8.7.6 Byte Count Registers (BCRs) ....................................................................... 8-21
8.7.7 DAR and BCR Values-Double PCI Write ................................................. 8-22
8.7.8 Next Descriptor Address Registers (NDARs) .............................................. 8-23
9.1 Message Unit (MU) Overview............................................................................ 9-1
9.2 Message and Doorbell Register Programming Model........................................ 9-2
9.2.1 Message and Doorbell Register Summary...................................................... 9-2
9.2.2 Message Register Descriptions....................................................................... 9-3
9.2.3 Doorbell Register Descriptions....................................................................... 9-3
9.3 I O Interface ....................................................................................................... 9-5
2
9.3.1 PCI Configuration Identification .................................................................... 9-5
9.3.2 I O Register Summary.................................................................................... 9-5
2
9.3.3 FIFO Descriptions........................................................................................... 9-6
9.3.3.1 Inbound FIFOs............................................................................................ 9-7
9.3.3.1.1
9.3.3.1.2
9.3.3.2 Outbound FIFOs ......................................................................................... 9-8
9.3.3.2.1
9.3.3.2.2
9.3.4 I O Register Descriptions ............................................................................... 9-9
2
9.3.4.1 PCI-Accessible I
9.3.4.1.1
9.3.4.1.2
9.3.4.1.3
9.3.4.1.4
9.3.4.2 Processor-Accessible I
9.3.4.2.1
9.3.4.2.2
9.3.4.2.3
9.3.4.2.4
9.3.4.2.5
CONTENTS
Chapter 9
Message Unit (with I
Inbound Free_List FIFO ......................................................................... 9-8
Inbound Post_List FIFO ......................................................................... 9-8
Outbound Free_List FIFO ...................................................................... 9-8
Outbound Post_List FIFO ...................................................................... 9-9
O Registers..................................................................... 9-9
2
Outbound Message Interrupt Status Register (OMISR)......................... 9-9
Outbound Message Interrupt Mask Register (OMIMR) ...................... 9-10
Inbound FIFO Queue Port Register (IFQPR)....................................... 9-11
Outbound FIFO Queue Port Register (OFQPR)................................... 9-12
O Registers ......................................................... 9-12
2
Inbound Message Interrupt Status Register (IMISR) ........................... 9-12
Inbound Message Interrupt Mask Register (IMIMR)........................... 9-14
Inbound Free_FIFO Head Pointer Register (IFHPR)........................... 9-15
Inbound Free_FIFO Tail Pointer Register (IFTPR) ............................. 9-16
Inbound Post_FIFO Head Pointer Register (IPHPR) ........................... 9-16
Contents
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