Completing An Exclusive Access - Motorola MPC8240 User Manual

PCI Error Functions

7.5.3 Completing an Exclusive Access

When an initiator is ready to complete an exclusive access, it should negate LOCK when
IRDY is negated following the completion of the last data phase of the locked operation.
This is to ensure that the target is released prior to any other operation and the resource is
no longer blocked.
7.5.4 Attempting to Access a Locked Target
If LOCK is asserted during the address phase to a locked target, the locked target signals a
retry, terminating the transaction without transferring any data. (The lock master always
negates LOCK during the address phase of a transaction to a locked target.) Nonlocked
targets ignore the LOCK signal when decoding the address. This allows other PCI agents
to initiate and respond to transactions while maintaining exclusive access to the locked
target.
7.5.5 Exclusive Access and the MPC8240
As an initiator, the MPC8240 does not generate locked operations. As a target, the
MPC8240 responds to locked operations by guaranteeing complete access exclusion to
local memory from the point-of-view of the PCI bus. From the point of view of the
processor core, only the cache line (32 bytes) of the transaction is locked.
If an initiator on the PCI bus asserts LOCK for a read transaction to local memory, the
MPC8240 completes the snoop transactions for any previous PCI-to-local-memory write
operations and performs a snoop transaction for the locked read operation on the internal
peripheral logic bus. Subsequent processor core accesses to local memory, when LOCK is
asserted, are permitted with the exception that if the processor core attempts to access
addresses within the locked cache line, the MPC8240 will retry the processor until the
locked operation is completed. If a locked operation covers more than one cache line
(32 bytes), only the most recently accessed cache line is locked from the processor. Since
a snoop transaction is required to establish a lock, the MPC8240 does not honor the
assertion of LOCK when PICR1[NO_SNOOP_EN] is set.
7.6 PCI Error Functions
PCI provides for parity and other system errors to be detected and reported. This section
describes generation and detection of parity and error reporting for the PCI bus.
The PCI command register and error enabling registers 1 and 2 provide for selective
enabling of specific PCI error detection. The PCI status register, error detection registers 1
and 2, the PCI bus error status register, and the 60x/PCI error address register provide PCI
error reporting. These registers are described in Chapter 4, "Configuration Registers."
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