Motorola MPC8240 User Manual page 182

Memory Control Configuration Registers
Table 4-41. Bit Settings for MCCR4—0xFC (Continued)
Bits Name
7–4 ACTORW
3–0 BSTOPRE[6–9]
4-54
Reset
Value
0000 Activate to read/write interval. For SDRAM only. These bits control the number
of clock cycles from an SDRAM-activate command until an SDRAM-read or
SDRAM-write command is allowed. See Section 6.2.4, "SDRAM Power-On
Initialization," for more information.
0001 Reserved
0010 2 clocks (minimum for flow-through or registered data interfaces)
0011 3 clocks (minimum for in-line ECC/parity data interfaces)
... ...
1111 15 clocks
0000 16 clocks
0000 Burst to precharge—bits 6–9. For SDRAM only. These bits, together with
BSTOPRE[0–1] (bits 19–18 of MCCR4), and BSTOPRE[2–5] (bits 31–28 of
MCCR3), control the open page interval. The page open duration counter is
reloaded with BSTOPRE[0–9] every time the page is accessed (including page
hits). When the counter expires, the open page is closed with a
SDRAM-precharge bank command. See Chapter 6, "MPC8240 Memory
Interface," for more information.
MPC8240 Integrated Processor User's Manual
Description