Mpc8240 Integrated Processor Core Block Diagram - Motorola MPC8240 User Manual

SYSTEM
REGISTER
UNIT
+
INTEGER
GPR File
UNIT
GP Rename
/ +
*
Registers
XER
COMPLETION
UNIT
Power Time Base
Dissipation Counter/
Control Decrementer
JTAG/COP Clock
Interface Multiplier
Touch Load Buffer
Copyback Buffer
Figure 1-5. MPC8240 Integrated Processor Core Block Diagram
64 Bit
SEQUENTIAL
FETCHER
64 Bit
INSTRUCTION
QUEUE
Dispatch Unit
64 Bit
64 Bit 64 Bit
LOAD/STORE
UNIT
+
32 Bit
D MMU
SRs
DBAT
Array
DTLB
16Kbyte
Tags
D Cache
32-Bit Address Bus
32-/64-Bit Data Bus
Chapter 1. Overview
Processor Core Overview
64 Bit
BRANCH
PROCESSING
UNIT
CTR
CR
LR
64 Bit
INSTRUCTION UNIT
64 Bit
FLOATING-
FPR File
POINT UNIT
FP Rename
/
*
Registers
FPSCR
I MMU
SRs
64 Bit
ITLB
Tags
PERIPHERAL LOGIC
BUS INTERFACE
+
IBAT
Array
16Kbyte
I Cache
1-9