Motorola MPC8240 User Manual page 604

PowerPC Register Set
Reset
Bit(s) Name
Value
14 TGPR 0
15 ILE 0
16 EE 0
17 PR 0
18 FP 0
19 ME 0
20 FE0 0
21 SE 0
22 BE 0
23 FE1 0
24 — 0
25 IP 1
26 IR 0
27 DR 0
E-14
Table E-8. MSR Bit Settings (Continued)
Temporary GPR remapping (603e-specific)
0 Normal operation
1 TGPR mode. GPR0–GPR3 are remapped to TGPR0–TGPR3 for use by TLB miss
routines.
The contents of GPR0–GPR3 remain unchanged while MSR[TGPR] = 1. Attempts to use
GPR4–GPR31 with MSR[TGPR] = 1 yield undefined results. When this bit is set, all
instruction accesses to GPR0–GPR3 are mapped to TGPR0–TGPR3, respectively. The
TGPR bit is set when an instruction TLB miss, data TLB miss on load or data TLB miss on
store exception is taken. The TGPR bit is cleared by an rfi instruction.
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception.
External interrupt enable
0 While the bit is cleared, the processor delays recognition of external interrupts and
decrementer exception conditions.
1 The processor is enabled to take an external interrupt or the decrementer exception.
Privilege level
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
Floating-point available
0 The processor prevents dispatch of floating-point instructions, including floating-point
loads, stores, and moves.
1 The processor can execute floating-point instructions.
Machine check enable
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
Floating-point exception mode 0 (see Table E-9).
Single-step trace enable
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception upon the successful execution of
the next instruction.
Branch trace enable
0 The processor executes branch instructions normally.
1 The processor generates a branch trace exception after completing the execution of a
branch instruction, regardless of whether the branch was taken.
Floating-point exception mode 1 (see Table E-9).
Reserved
Exception prefix. The setting of this bit specifies whether an exception vector offset is
prepended with Fs or 0s. In the following description, nnnnn is the offset of the exception
vector.
0 Exceptions are vectored to the physical address 0x000n_nnnn.
1 Exceptions are vectored to the physical address 0xFFFn_nnnn.
In most systems, IP is set to 1 during system initialization, and then cleared to 0 when
initialization is complete.
Instruction address translation
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.
Data address translation
0 Data address translation is disabled.
1 Data address translation is enabled.
MPC8240 Integrated Processor User's Manual
Description