Hardware Implementation-Dependent Register 1 (Hid1) - Motorola MPC8240 User Manual

Programming Model
Table 5-1. HID0 Field Descriptions (Continued)
Bits Name
24 — IFEM bit on some other PowerPC devices
This bit is not used in the MPC8240 (and so it is reserved).
25–26 — Reserved
27 FBIOB Force branch indirect on bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally.
28 — Reserved—Used as address broadcast enable bit on some other PowerPC devices
29–30 — Reserved
31 NOOPTI No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled.
1 The dcbt and dcbtst instructions are no-oped globally.
1
See Chapter 9, "Power Management," of the MPC603e User's Manual for more information.
2
See Chapter 3, "Instruction and Data Cache Operation," of the MPC603e User's Manual for more information.
Table 5-2 shows how HID0[SBCLK], HID0[ECLK], and the hard reset signals are used to
configure CKO when PMCR1[CKO_SEL] = 0. When PMCR1[CKO_SEL] = 1, the
CKO_MODE field of PMCR1 determines the signal driven on CKO. Note that the initial
value of PMCR1[CKO_SEL] is determined by the value on the AS signal at the negation
of HRST_CPU. See Section 2.2.7.8, "Debug Clock (CKO)—Output," and Section 2.4,
"Configuration Signals Sampled at Reset," for more information.
Table 5-2. HID0[BCLK] and HID0[ECLK] CKO Signal Configuration
HRST_CPU
and
HRST_CTRL
Asserted
Negated
Negated
Negated
Negated

5.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)

The MPC8240 implementation of HID1 is shown in Figure 5-4.
PLLRATIO
0 1 2 3 4 5
Figure 5-4. Hardware Implementation Register 1 (HID1)
5-16
HID0[ECLK] HID0[SBCLK]
x
0
0
1
1
MPC8240 Integrated Processor User's Manual
Description
Signal Driven on CKO
x Processor core clock
0 High impedance
1 sys-logic-clk divided by 2
0 Processor core clock
1 sys-logic-clk
—
31