Epic Interrupt Configuration Register (Eicr) - Motorola MPC8240 User Manual

Table 11-6 describes the bit settings for the GCR.
Table 11-6. GCR Field Descriptions—Offset 0x4_1020
Reset
Bits Name
Value
31 R 0
30 — 0
29 M 0
28–0 — All 0s
11.9.3 EPIC Interrupt Configuration Register (EICR)
The EICR provides programming control for the serial interrupt mode and the serial clock
frequency. Note that this register is read/write. Figure 11-6 shows the bits in the EICR.
SIE
0 R
31 30 28 27 26
Figure 11-6. EPIC Interrupt Configuration Register (EICR)
Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
Reset EPIC unit. Writing a one to this bit resets the EPIC controller logic. This bit is
cleared automatically when this reset sequence is complete. Setting this bit causes the
following:
• All pending and in-service interrupts are cleared.
• All interrupt mask bits are set.
• All timer base count values are reset to zero and count inhibited.
• The processor current task priority is reset to 0xF thus disabling interrupt delivery to
the processor.
• Spurious vector resets to 0xFF.
• EPIC defaults to pass-through mode.
• The serial clock ratio resets to 0x4.
All other registers remain at their pre-reset programmed values.
Reserved
Mode
0 Pass-through mode. EPIC is disabled and interrupts detected on IRQ0 (active-high)
are passed directly to the processor core.
1 Mixed-mode. When this bit is set, EICR[SIE] determines whether the EPIC unit is
operating in direct or serial interrupts mode.
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
Register Definitions
Reserved
0
11-17