D.1 Instructions Sorted By Mnemonic - Motorola MPC8240 User Manual

Appendix D
PowerPC Instruction Set Listings
This appendix lists the MPC8240 microprocessor's instruction set as well as the additional
PowerPC instructions not implemented in the MPC8240. Instructions are sorted by
mnemonic, opcode, function, and form. Also included in this appendix is a quick reference
table that contains general information, such as the architecture level, privilege level, and
form, and indicates if the instruction is 64-bit and optional.
Note that split fields, that represent the concatenation of sequences from left to right, are
shown in lowercase. For more information refer to Chapter 8, "Instruction Set," in The
Programming Environments Manual.

D.1 Instructions Sorted by Mnemonic

Table D-1 lists the instructions implemented in the PowerPC architecture in alphabetical
order by mnemonic.
Table D-1. Complete Instruction List Sorted by Mnemonic
Key:
Reserved bits
Name
0
addx 31
addcx 31
addex 31
addi 14
addic 12
addic. 13
addis 15
addmex 31
addzex 31
andx 31
andcx 31
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D A
D A
D A
D A
D A
D A
D A
D A
D A
S A
S A
Appendix D. PowerPC Instruction Set Listings
Instruction not implemented in the MPC8240
B OE
B OE
B OE
SIMM
SIMM
SIMM
SIMM
0 0 0 0 0 OE
0 0 0 0 0 OE
B
B
266 Rc
10 Rc
138 Rc
234 Rc
202 Rc
28 Rc
60 Rc
D-1