Motorola MPC8240 User Manual page 34

Integrated host processor with integrated pci
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Table
Number
9-9
OMISR Field Descriptions-Offset 0x030 ................................................................ 9-10
9-10
OMIMR Field Descriptions-Offset 0x034 ............................................................... 9-11
9-11
IFQPR Field Descriptions-Offset 0x040.................................................................. 9-12
9-12
OFQPR Field Descriptions-Offset 0x044 ................................................................ 9-12
9-13
IMISR Field Descriptions-Offset 0x0_0100 ............................................................ 9-13
9-14
IMIMR Field Descriptions-Offset 0x0_0104........................................................... 9-15
9-15
IFHPR Field Descriptions-Offset 0x0_0120............................................................ 9-16
9-16
IFTPR Field Descriptions-Offset 0x0_0128 ............................................................ 9-16
9-17
IPHPR Field Descriptions-Offset 0x0_0130............................................................ 9-17
9-18
IPTPR Field Descriptions-Offset 0x0_0138 ............................................................ 9-17
9-19
OFHPR Field Descriptions-Offset 0x0_0140 .......................................................... 9-18
9-20
OFTPR Field Descriptions-Offset 0x0_0148........................................................... 9-19
9-21
OPHPR Field Descriptions-Offset 0x0_0150 .......................................................... 9-19
9-22
OPTPR Field Descriptions- Offset 0x0_0158.......................................................... 9-20
9-23
MUCR Field Descriptions- Offset 0x0_0164 .......................................................... 9-20
9-24
QBAR Field Descriptions- Offset 0x0_0170 ........................................................... 9-21
2
10-1
I
C Interface Signal Description................................................................................. 10-2
2
10-2
I
C Register Summary ................................................................................................ 10-2
10-3
I2CADR Field Descriptions-Offset 0x0_3000......................................................... 10-8
10-4
I2CFDR Field Descriptions-Offset 0x0_3004 ......................................................... 10-8
10-5
Serial Bit Clock Frequency Divider Selections .......................................................... 10-9
10-6
I2CCR Field Descriptions-Offset 0x0_3008.......................................................... 10-10
10-7
I2CSR Field Descriptions-Offset 0x0_300C.......................................................... 10-12
10-8
I2CDR Field Descriptions-Offset 0x0_3010.......................................................... 10-13
11-1
EPIC Interface Signal Description.............................................................................. 11-2
11-2
EPIC Register Address Map-Global and Timer Registers....................................... 11-4
11-3
EPIC Register Address Map-Interrupt Source Configuration Registers.................. 11-5
11-4
EPIC Register Address Map-Processor-Related Registers ...................................... 11-7
11-5
FRR Field Descriptions-Offset 0x4_1000.............................................................. 11-16
11-6
GCR Field Descriptions-Offset 0x4_1020............................................................. 11-17
11-7
EICR Field Descriptions-Offset 0x4_1030 ............................................................ 11-18
11-8
EVI Register Field Descriptions-Offset 0x4_1080 ................................................ 11-18
11-9
PI Register Field Descriptions-Offset 0x4_1090 ................................................... 11-19
11-10
SVR Field Descriptions-Offset 0x4_10E0............................................................. 11-20
11-11
TFRR Field Descriptions-Offset 0x4_10F0........................................................... 11-20
11-12
EUMBBAR Offsets for GTCCRs............................................................................. 11-21
11-13
GTCCR Field Descriptions....................................................................................... 11-21
11-14
EUMBBAR Offsets for GTBCRs............................................................................. 11-21
11-15
GTBCR Field Descriptions....................................................................................... 11-22
11-16
EUMBBAR Offsets for GTVPRs............................................................................. 11-22
11-17
GTVPR Field Descriptions ....................................................................................... 11-23
11-18
EUMBBAR Offsets for GTDRs ............................................................................... 11-23
11-19
GTDR Field Descriptions ......................................................................................... 11-24
xxxiv
TABLES
Title
MPC8240 Integrated Processor User's Manual
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