Dram Single-Beat Read Timing (No Ecc) - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
Figure 6-35 through Figure 6-40 shows FPM or EDO timing for various types of accesses
with ECC disabled.
Figure 6-35 shows a single-beat read operation
.
MCLK
RAS
CAS
ADDR
DATA
WE
Figure 6-35. DRAM Single-Beat Read Timing (No ECC)
Figure 6-36 shows a 64-bit bus mode burst read operation.
MCLK
RP 1
CRP
RAS
CAS
ASR
ADDR
DATA
WE
Figure 6-36. DRAM Four-Beat Burst Read Timing (No ECC)—64-Bit Mode
6-58
RP 1
CRP
CP
ASR
ROW
RC
RCD 2
CAS 3 CP 4
CP
CSH
RAH ASC CAH
ROW COL
RAD
AA
D0
RAC
CAC
MPC8240 Integrated Processor User's Manual
RAS
RC
RCD 2 CAS 3
CSH
RSH
RAL
RAH ASC CAH
COL
AA
RAD
D0
RAC
CAC
RASP
CAS 5
CP 4 CAS 5
PC
CAH
COL COL
AA AA
D1 D2
CAC CAC
CP 4 CAS 5
RSH
RAL
COL
RHCP
AA
D3
CAC