Peripheral Logic Functional Units - Motorola MPC8240 User Manual

Peripheral Logic Overview
— Decoupled address and data buses for pipelining of peripheral logic bus accesses
— Store gathering on peripheral logic bus-to-PCI writes
• Memory interface
— 1 Gbyte of RAM space, 16 Mbytes of ROM space
— High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
— Supports fast page mode DRAMs, extended data out (EDO) DRAMs, or
synchronous DRAMs (SDRAMs)
— Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 1 to
128 Mbytes per bank
— Supports page mode SDRAMs—four open pages simultaneously
— DRAM/EDO configurations support parity or error checking and correction
(ECC); SDRAM configurations support ECC
— ROM space may be split between the PCI bus and the memory bus (8 Mbytes
each)
— Supports 8-bit asynchronous ROM, or 32- or 64-bit burst-mode ROM
— Supports writing to flash ROM
— Configurable data path
— Programmable interface timing
• PCI interface
— Compatible with PCI Local Bus Specification, Revision 2.1
— Supports PCI locked accesses to memory using the LOCK signal and protocol
— Supports accesses to all PCI address spaces
— Selectable big- or little-endian operation
— Store gathering on PCI writes to memory
— Selectable memory prefetching of PCI read accesses
— Interface operates at up to 66 MHz
— Parity support
• Supports concurrent transactions on peripheral logic bus and PCI buses

1.4.2 Peripheral Logic Functional Units

The peripheral logic consists of the following major functional units:
• Peripheral logic bus interface
• Memory interface
• PCI interface
— PCI bus arbitration unit
— Address maps and translation
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