Motorola MPC8240 User Manual page 622

Memory consistency. Refers to levels of memory with respect to a single
Memory-forced I/O controller interface access. These accesses are made
Memory management unit. The functional unit in the 603e that translates
Modified state. EMI state (M) in which one, and only one, caching device
N O
Out-of-order. An operation is said to be out-of-order when it is not
P _____________________________________________________________
Page. A 4-Kbyte area of memory, aligned on a 4-Kbyte boundary.
Park. The act of allowing a bus master to maintain mastership of the bus
Pipelining. A technique that breaks instruction execution into distinct steps
Q
Quiesce. To come to rest. The processor is said to quiesce when an exception
Glossary-4
processor and system memory (for example, on-chip cache,
secondary cache, and system memory).
to memory space. They do not use the extensions to the memory
protocol described for I/O controller interface accesses, and they
bypass the page- and block-translation and protection mechanisms.
the logical address bits to physical address bits.
has the valid data for that address. The data at this address in external
memory is not valid.
guaranteed to be required by the sequential execution model, such as
the execution of an instruction that follows another instruction that
may alter the instruction flow. For example, execution of instructions
in an unresolved branch is said to be out-of-order, as is the execution
of an instruction behind another instruction that may yet cause an
exception. The results of operations that are performed out-of-order
are not committed to architected resources until it can be ensured that
these results adhere to the in-order, or sequential execution model.
without having to arbitrate.
so that multiple steps can be performed at the same time.
is taken or a sync instruction is executed. The instruction stream is
stopped at the decode stage and executing instructions are allowed to
complete to create a controlled context for instructions that may be
affected by out-of-order, parallel execution. See Context
synchronization.
MPC8240 Integrated Processor User's Manual