E.1 Powerpc Register Set - Motorola MPC8240 User Manual

Appendix E
Processor Core Register Summary
This appendix summarizes the register set in the processor core of the MPC8240 as defined
by the three programming environments of the PowerPC architecture—the user instruction
set architecture (UISA), the virtual environment architecture (VEA), and the operating
environment architecture (OEA), as well as the implementation-specific registers from the
MPC603e and the MPC8240-specific registers.
The register formats and bit descriptions in this appendix are intended only as a reference.
There are many details important for the programming of the processor core registers, such
as synchronization requirements and bit interactions, that are not supplied here. Full
descriptions of the basic register set defined by the PowerPC architecture are provided in
Chapter 2, "PowerPC Register Set," in The Programming Environments Manual.
Additionally, more complete descriptions of the processor core registers that are part of the
MPC603e are provided in Chapter 2, "Programming Model," in the MPC603e User's
Manual. See those references for important details about the registers and individual bits.

E.1 PowerPC Register Set

The PowerPC architecture defines register-to-register operations for all computational
instructions. Source data for these instructions is accessed from the on-chip registers or is
provided as an immediate value embedded in the opcode. The three-register instruction
format allows specification of a target register distinct from the two source registers, thus
preserving the original data for use by other instructions and reducing the number of
instructions required for certain operations. Data is transferred between memory and
registers with explicit load and store instructions only.
Figure E-1 shows the complete MPC8240 register set and the programming environment
to which each register belongs. This figure includes both the PowerPC register set and the
MPC8240-specific registers.
Note that there may be registers common to other PowerPC processors that are not
implemented in the MPC8240's processor core. Unsupported special purpose register
(SPR) values are treated as follows:
• Any mtspr with an invalid SPR executes as a no-op.
• Any mfspr with an invalid SPR causes boundedly undefined results in the target
register.
Appendix E. Processor Core Register Summary E-1