Epic Features Summary - Motorola MPC8240 User Manual

EPIC Unit Overview

11.1.1 EPIC Features Summary

The EPIC unit of the MPC8240 implements the following features:
• OpenPIC programming model
• Support for five external interrupt sources or one serial-style interrupt (16 interrupt
sources)
• Four global, cascadable, high-resolution timers that can be interrupt sources
• Interrupt control for the MPC8240 I
unit (MU)
• Support for connection of external interrupt controller device such as an 8259
Programmable Interrupt Controller (PIC)
• In 8259 (pass-through) mode, it generates local (internal) interrupts output signal,
L_INT.
• Processor initialization control—The processor can reset itself by setting the
processor initialization register, causing the assertion of the internal sreset signal as
described in Section 11.9.5, "Processor Initialization Register (PI)."
• Programmable resetting of the EPIC unit through the global configuration register
• 16 programmable interrupt priority levels
• Fully-nested interrupt delivery
• Spurious vector generation
• 32-bit configuration registers that are aligned on 128-bit boundaries
11.1.2 EPIC Interface Signal Description
In addition to the int signal, the external EPIC signals are defined in Table 11-1.
Signal Name Pins
IRQ0/S_INT
IRQ1/S_CLK
IRQ2/S_RST
11-2
Table 11-1. EPIC Interface Signal Description
I/O
1 I Direct IRQ mode—Input representing an incoming interrupt request.
Serial IRQ mode—Input representing the serial interrupt data stream.
Note that the IRQ0 is used when operating in the pass-through mode.
1 I/O Direct IRQ mode—Input representing an incoming interrupt request
Serial IRQ mode—Output representing the serial clock by which the
remote sequencer (interrupt source) clocks serial interrupts out.
1 I/O Direct IRQ mode—Input representing an incoming interrupt request
Serial IRQ mode—Output pulse is active after EPIC resets and is set to
serial mode. It determines the serial interrupt slot count for all external
serial devices. Refer to Figure 11.7.
MPC8240 Integrated Processor User's Manual
2
C unit, DMA unit (2 channels), and message
State Meaning