E.1.3.7 Dsisr - Motorola MPC8240 User Manual

E.1.3.7 DSISR

The 32-bit DSISR is shown in Figure E-17.
0
For information about bit settings, see Chapter 4, "Exceptions," in the MPC603e User's
Manual.
E.1.3.8 Machine Status Save/Restore Register 0 (SRR0)
The format of SRR0 is shown in Figure E-18.
0
Figure E-18. Machine Status Save/Restore Register 0 (SRR0)Machine Status
The format of SRR1 is shown in Figure E-19.
0
Figure E-19. Machine Status Save/Restore Register 1 (SRR1)
E.1.3.9 Time Base Facility (TB)—OEA; Writing to the Time Base
Note that writing to the TB is reserved for supervisor-level software.
The simplified mnemonics, mttbl and mttbu, write the lower and upper halves of the TB,
respectively. The simplified mnemonics listed above are for the mtspr instruction. The
mtspr, mttbl, and mttbu instructions treat TBL and TBU as separate 32-bit registers;
setting one leaves the other unchanged. It is not possible to write the entire 64-bit time base
with a single instruction.
E.1.3.10 Decrementer Register (DEC)
The decrementer register (DEC), shown in Figure E-20, is a 32-bit decrementing counter
that is decremented once every four sys_logic_clk cycles and provides a mechanism for
causing a decrementer exception after a programmable delay.
DSISR
Figure E-17. DSISR
SRR0
Save/Restore Register 1 (SRR1)
SRR1
Appendix E. Processor Core Register Summary
PowerPC Register Set
31
Reserved
00
29 30 31
31
E-19