Dma Register Summary - Motorola MPC8240 User Manual

DMA Register Summary

Figure 8-1 provides a block diagram of the MPC8240 DMA unit.
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8.2 DMA Register Summary
There are two complete sets of DMA registers on the MPC8240—one for channel 0 and
one for channel 1.
The DMA registers of the MPC8240 comprise part of the MPC8240 embedded utilities and
are memory mapped. The base addresses for the DMA registers are determined by the
PCSRBAR for accesses from PCI memory space and the EUMBBAR for accesses from
local memory. See Section 3.4, "Embedded Utilities Memory Block (EUMB)," for more
information.
The two DMA channels on the MPC8240 are identical, except that the registers for channel
0 are located at offsets 0x100 and 0x0_1100, and the registers for channel 1 are located at
offsets 0x200 and 0x0_1200. Throughout this chapter, the registers are described by a
singular acronym (for example, DMR stands for the mode register for either channel 0 or
channel 1). Table 8-1 summarizes the DMA registers on the MPC8240. All DMA registers
are 32 bits wide and are accessible from the processor or remote PCI masters in both host
and agent mode as shown.
8-2
64 bytes
To memory interface
PCI Interface Unit
Figure 8-1. DMA Controller Block Diagram
MPC8240 Integrated Processor User's Manual
DMA 1 DMA 0
Queue Queue
Interface logic
PCI Bus